1. Field of the Invention
This invention relates to a multichip module (MCM), and more specifically to a multichip module having a stacked chip arrangement.
2. Description of the Related Art
As electronic devices have become more smaller and thinner, the packages for protecting and interconnecting IC chips have the same trend, too.
With ever increasing demands for miniaturization and higher operating speeds, multichip modules (MCMs) are increasingly attractive in a variety of electronics. MCMs which contain more than one die can help minimize the system operational speed restrictions imposed by long printed circuit board connection traces by combining, for example, the processor, memory, and associated logic into a single package. In addition, MCMs decrease the interconnection length between IC chips thereby reducing signal delays and access times.
The most common MCM is the xe2x80x9cside-by-sidexe2x80x9d MCM. In this version two or more IC chips are mounted next to each other (or side by side each other) on the principal mounting surface of a common substrate. Interconnections among the chips and conductive traces on the substrate are commonly made via wire bonding. The side-by-side MCM, however, suffers from a disadvantage that the package efficiency is very low since the area of the common substrate increases with an increase in the number of semiconductor chips mounted thereon.
Therefore, U.S. Pat. No. 5,323,060 teaches a multichip stacked device (see FIG. 1) comprising a first semiconductor chip 110 attached to a substrate 120 and a second semiconductor chip 130 stacked atop the first semiconductor chip 110. The chips 110, 120 are respectively wire bonded to the substrate 120. U.S. Pat. No. 5,323,060 characterized by using an adhesive layer 140 between the two chips to provide clearance between the chips for the loops of the bonding wires. The wire bonding process of the underlying chip 110 must be completed before the chip 130 can be stacked on the chip 110. This means that the die bonding process must be repeated for each additional layer of the stack. In addition to adding extra process steps, there is a chance of damaging the underlying wires. Additionally, the clearances between two adjacent chips in the stack are quite tight. This will lead to limited processing window in wire binding process, thereby creating reliability problems of the bonding wires.
Accordingly, it is a primary object of the present invention to provide a multichip module which allows at least two chips in a stack to be attached to the substrate prior to wire bonding.
It is another object of the present invention to provide a multichip module which does not restrict the loop height for the underlying chip, thereby allowing a larger processing window during wire bonding, thereby enhancing the reliability of bonding wires for the underlying chip.
It is a further object of the present invention to provide a multichip module which does not restrict the loop height for the underlying chip, thereby allowing thinner layers of adhesive separating the chips, and reducing the overall height of the assembly.
The multichip module according to a preferred embodiment of the present invention mainly comprises at least two semiconductor chips wherein each has a row of bonding pads formed on the active surface thereof and disposed along one side edge thereof. The semiconductor chips are mounted to a substrate in a stacking arrangement wherein the upper chip is attached to the active surface of the lower chip in a manner that no portion of the upper chip interferes with a vertical line of sight of each bond pad of the lower chip to permit wire bonding thereof. The wire bonding process of the semiconductor chips are performed after stacking the chips on the substrate. Therefore, the multichip module having a stacked chip arrangement in accordance with the present invention characterized in that wire bonding of chips can be completed in a single step so as to increase UPH (unit per hour), thereby reducing cost for manufacturing the MCM.
Further, since no portion of the upper chip interferes with a vertical line of sight of each bond pad of the lower chip, the upper chip does not restrict the loop height for the lower chip. This provides a larger processing window during wire bonding thereby enhancing the reliability of bonding wires for the underlying chip, and allows thinner layers of adhesive separating the chips thereby reducing the overall height of the assembly.